Published by: sadikshya
Published date: 24 Jun 2021
Fall 2016 Digital Systems
This is the question set along with the answers of Fall 2016 Digital Systems which was taken by the Pokhara University (PU).
POKHARA UNIVERSITY
Fall 2016 Digital Systems
| Level: Bachelor | Semester – Fall | Year: 2016 |
| Program: BCIS | Full Marks: 100 | |
| Course: Digital Systems | Pass Marks: 45 | |
| Time:3hrs | ||
| Candidates are required to give their answers in their own words as far as practicable. | ||
| The figures in the margin indicate full marks. | ||
Section “A”
Very Short Answer Questions
| Attempt all the questions. | 10×2 | |
| 1 | What do you mean by a digital system? | 2 |
| 2 | What do you understand by TTL, ECL, FET, and MOSFET? | 2 |
| 3 | Write down the characteristic equation of T flip-flop. | 2 |
| 4 | What are Flipflops? | 2 |
| 5 | What are counters? | 2 |
| 6 | Which gates are called universal gates? Why? | 2 |
| 7 | Express the decimal number-225 in sign-magnitude form, 1’s complement form, and 2’s complement form. | 2 |
| 8 | Explain Multiplexer. | 2 |
| 9 | What is ALU? | 2 |
| 10 | What weight does 3 have in a hexadecimal number (12345)16? | 2 |
Section “B”
Descriptive Answer Questions
| Attempt any six questions | 6×10 | |
| 11 | Realize the following function using minimum number of universal gates. F (A, B, C, D ) = ∑(0, 2, 3, 4,8,9,12,13,15) | |
| 12 | What are the fundamental differences between Combinational Circuits and Sequential Circuits? Show the complete design of a full subtractor circuit. | |
| 13 | Explain Binary Parallel Adder. Design Full Adder using two half adder and OR gate | |
| 14 | What do you understand by triggering of Flip-flop? Show the next state table of RS, JK, D, and T flip-flops. | |
| 15 | Design a 3-bit Synchronous Counter. | |
| 16 | What is a bus organization? Explain with an example how arithmetic and logical operations are done by ALU. | |
| 17 | Explain the technologies used for IC Fabrication. What are the different levels of Integration? |
Section “C”
| Case Analysis | |||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | a) Explain different types of Shift Register with a clean diagram.
b) Reduce the number of states in the following state table and tabulate the reduced state table
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